Teraspeed® consultants have engineered the toughest of packaging challenges. From characterization of packages for SSO and crosstalk concerns, to designing advanced OC-48, XAUI and OC-192 packages that operate at 2.5, 3.125, 10 and 40 Gbps, we bring our knowledge to your design. We offer the following value to your team:

• I/O Buffer Sizing - Before silicon has been taped out, we work with custom, semi-custom and ASIC designers to validate the performance in-package & in-system of devices before they are commited to history. Our recommendations have rescued clients from disaster, accelerated time to market and saved millions of dollars.
• Package Characterization - Teraspeed® engineers evaluate packages for signal integrity, timing, noise, power delivery and resonance concerns in the system and under the configurations that occur in actual design practice. With our processes we model, simulate and analyze the package as a system element for all design margins, documented and ready to correlate to measurements. If you want, we can carry the process into the lab for final measurements and verification.
• Package Design - Using advanced full-wave, quasi-static and hybrid modeling techniques, Teraspeed® consultants will design all or part of a package. Our designs meet or exceed performance objectives and stand head and shoulders above most in the industry. We provide superior value and extreme performance at 3.125 and 10 Gbps.
• Design Kits - Teraspeed® engineers provide package design kits tailored to your needs, complete with design guidelines and rules, along with expert consultation. We enable you to meet your schedules and performance objectives.

 

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